//------------------------------------------------------------------------------
// Copyright (c) 2012 by Silicon Laboratories.
// All rights reserved. This program and the accompanying materials
// are made available under the terms of the Silicon Laboratories End User
// License Agreement which accompanies this distribution, and is available at
// http://developer.silabs.com/legal/version/v10/License_Agreement_v10.htm
// Original content and implementation provided by Silicon Laboratories.
//------------------------------------------------------------------------------

//==============================================================================
// WARNING:
//
// This file is auto-generated by AppBuilder and should not be modified.
// Any hand modifications will be lost if the project is regenerated.
//==============================================================================
// library
// hal
#include <si32_device.h>
#include <SI32_CLKCTRL_A_Type.h>
#include <SI32_UART_B_Type.h>
// application
#include "gUART0.h"

//==============================================================================
//CONFIGURATION FUNCTIONS
//==============================================================================
void gUART0_enter_off_config(void)
{
   // DISABLE UART0 CLOCK
   SI32_CLKCTRL_A_disable_apb_to_modules_0(SI32_CLKCTRL_0,
                                                    SI32_CLKCTRL_A_APBCLKG0_UART0);
}

//------------------------------------------------------------------------------
void gUART0_enter_async_apb_config()
{
   // ENABLE UART0 CLOCK
   SI32_CLKCTRL_A_enable_apb_to_modules_0(SI32_CLKCTRL_0,
                                                   SI32_CLKCTRL_A_APBCLKG0_UART0);
   SI32_CLKCTRL_A_enable_apb_to_modules_1(SI32_CLKCTRL_0,
                                         SI32_CLKCTRL_A_APBCLKG1_MISC0);
   // SETUP UART. BAUD RATE (APB = System Clock)
   SI32_UART_B_enter_full_duplex_mode(SI32_UART_0);
   
	// Standard Mode (APB Clock Source) (115200 baud)
   SI32_UART_B_select_apb_clock_mode(SI32_UART_0);
   SI32_UART_B_set_tx_baudrate(SI32_UART_0, (SystemCoreClock / (2 * 115200)) - 1);
   SI32_UART_B_set_rx_baudrate(SI32_UART_0, (SystemCoreClock / (2 * 115200)) - 1);
   
   // SETUP TX (8-bit, 1stop, no-parity)
   SI32_UART_B_select_tx_data_length(SI32_UART_0, 8);
   SI32_UART_B_enable_tx_start_bit(SI32_UART_0);
   SI32_UART_B_enable_tx_stop_bit(SI32_UART_0);
   SI32_UART_B_disable_tx_parity_bit(SI32_UART_0);
   SI32_UART_B_select_tx_stop_bits(SI32_UART_0, SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE);
   SI32_UART_B_disable_tx_signal_inversion(SI32_UART_0);
   SI32_UART_B_enable_tx_output(SI32_UART_0);
   SI32_UART_B_enable_tx(SI32_UART_0);

   // SETUP RX
   SI32_UART_B_select_rx_data_length(SI32_UART_0, 8);
   SI32_UART_B_enable_rx_start_bit(SI32_UART_0);
   SI32_UART_B_enable_rx_stop_bit(SI32_UART_0);
   SI32_UART_B_select_rx_stop_bits(SI32_UART_0, SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE);
   SI32_UART_B_disable_rx_signal_inversion(SI32_UART_0);
   SI32_UART_B_select_rx_fifo_threshold_1(SI32_UART_0);
   SI32_UART_B_enable_rx(SI32_UART_0);

   SI32_UART_B_write_clkdiv(SI32_UART_0,0);

}

//------------------------------------------------------------------------------
void gUART0_enter_async_rtc_config()
{
   // ENABLE UART0 CLOCK
   SI32_CLKCTRL_A_enable_apb_to_modules_0(SI32_CLKCTRL_0,
                                                   SI32_CLKCTRL_A_APBCLKG0_UART0);
   SI32_CLKCTRL_A_enable_apb_to_modules_1(SI32_CLKCTRL_0,
                                         SI32_CLKCTRL_A_APBCLKG1_MISC0);
   // SETUP UART. BAUD RATE (APB = System Clock)
   SI32_UART_B_enter_full_duplex_mode(SI32_UART_0);
   
	 // RTC Timer Clock Modes (9600 baud)
   SI32_UART_B_select_rtc_clock_mode(SI32_UART_0);
   SI32_UART_B_set_tx_baudrate(SI32_UART_0, 0x03);
   SI32_UART_B_set_rx_baudrate(SI32_UART_0, 0x03);

   // SETUP TX (8-bit, 1stop, no-parity)
   SI32_UART_B_select_tx_data_length(SI32_UART_0, 8);
   SI32_UART_B_enable_tx_start_bit(SI32_UART_0);
   SI32_UART_B_enable_tx_stop_bit(SI32_UART_0);
   SI32_UART_B_disable_tx_parity_bit(SI32_UART_0);
   SI32_UART_B_select_tx_stop_bits(SI32_UART_0, SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE);
   SI32_UART_B_disable_tx_signal_inversion(SI32_UART_0);
   SI32_UART_B_enable_tx_output(SI32_UART_0);
   SI32_UART_B_enable_tx(SI32_UART_0);

   // SETUP RX
   SI32_UART_B_select_rx_data_length(SI32_UART_0, 8);
   SI32_UART_B_enable_rx_start_bit(SI32_UART_0);
   SI32_UART_B_enable_rx_stop_bit(SI32_UART_0);
   SI32_UART_B_select_rx_stop_bits(SI32_UART_0, SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE);
   SI32_UART_B_disable_rx_signal_inversion(SI32_UART_0);
   SI32_UART_B_select_rx_fifo_threshold_1(SI32_UART_0);
   SI32_UART_B_enable_rx(SI32_UART_0);

   SI32_UART_B_write_clkdiv(SI32_UART_0,0);

}
//-eof--------------------------------------------------------------------------
